1. Field of the Invention
The invention relates to flash memories, and more particularly, to an improved method for erasing flash memories and related system thereof.
2. Description of the Prior Art
Flash memory is a memory device that allows multiple data writing, reading, and erasing operations. In addition, the stored data will be retained by the flash memory even after power to the device is removed. With these advantages, the utilization of flash memory has been broadly applied in personal computer and electronic equipment.
Please refer to FIG. 1, which is a schematic cross-section diagram of a conventional flash memory cell 100. As shown in FIG. 1, the flash memory cell 100 comprises a deep N-well region 110, a P-well region 120, a source region 130, a drain region 140, a floating gate 150, and a control gate 160. Generally speaking, the floating gate 150 and the control gate 160 can be fabricated using doped polysilicon. The control gate 160 is set up above the floating gate 150 with an inter-gate dielectric layer (not shown) separating the two gates. Furthermore, a tunneling oxide layer (not shown) is also setup between the floating gate and an underlying substrate (the so-called stack gate flash memory).
To write data into the flash memory cell 100, a bias voltage is applied to the control gate 160 and the source/drain regions 130/140 so that an electric field is set up to inject electrons into the floating gate 150. On the other hand, to read data from the flash memory cell 100, an operating voltage is applied to the control gate 160. Since the entrapment of charges inside the floating gate 150 will directly affect the opening or closing of the underlying channel between the source region 130 and the drain region 140, the opening or closing of the channel can be construed as a digital value of “1” or “0”. Finally, to erase data from the flash memory 100, the relative potential between the P-well region 120 and the control gate 160 is raised. Hence, a tunneling effect can be utilized to transfer electrons from the floating gate to the P-well region 120 via the tunneling oxide layer or from the floating gate to the control gate via the inter-gate dielectric layer.
Please refer to FIG. 2, which is a diagram of the voltages of the P-well region/deep N-well region 120/110 and the control gate 160 according to the prior art. As shown in FIG. 2, when the erase operation is performed, the P-well region 120 and the deep N-well region 110 are coupled to a high voltage, and the control gate 160 is coupled to a ground voltage. The voltage difference between the voltage of the P-well region 120 and the voltage of the control gate 160 is the erase voltage. That is, if the erase voltage is large enough to trigger the tunneling effect, the erasing operation starts. Therefore, in FIG. 2, when the erase voltage is not large enough, the entire flash memory cell is in a setup time, and when the erase voltage is large enough, the entire flash memory cell is in an erase time. In general, a controlling circuit (e.g., state machine) is often utilized to control the start time of the setup time and the ending of the erase time by coupling the voltages of the P-well and deep N-well to a high voltage or a ground voltage.
However, a problem exists in that the controlling circuit (i.e., state machine) cannot determine the definite timing when the erase operation starts. As mentioned previously, the erasing operation starts as long as the erase voltage is large enough. But the erase voltage may be influenced by a lot of factors (for example, the environments of different flash memory, the array loading, or the high voltage power source), this may cause the flash memory cell 100 to be erased too much or not enough so that a following writing operation or a reading operation cannot be performed correctly because the threshold voltage of the flash memory cell 100 depends on the erasing degree, and the current is controlled by the threshold voltage, the reading operation and writing operation is influenced.
In addition, when the erasing operation is performed completely, the voltages of the Deep N-well and P-well are both discharged. Furthermore, when a next erasing operation starts, the voltages of the Deep N-well and P-well must be charged again. However, if the operation of charging the voltages of the Deep N-well and P-well must be performed for every erasing operation, then a lot of time and additional power are consumed.
Furthermore, as is known, a plurality of memory cells is arranged in an array. For example, a flash memory comprises a plurality of memory blocks, where each memory block comprises the above-mentioned flash memory cells 100. Please note that the control gate of each flash memory cell 100 is coupled to a word line. Therefore, in the above disclosure, the control gate is coupled to a ground voltage (or a high voltage) via the word line.
Except for the flash memory cells 100, each memory block often comprises multiple dummy cells. The multiple dummy cells are formed on both sides of the memory block. Dummy cells, as the name implies, are utilized as fake flash memory cells. Because the edge of the memory block often encounters different environments from those of the inner memory cells inside the memory block, the dummy cells generate currents when other memory cells are being read. In other words, even the dummy word line (the dummy word line is a word line coupled to the dummy cells) is not biased; the dummy cells still output currents such that the bit line corresponding to each dummy cell has current. Obviously, this influences the reading operation of the entire flash memory.
In the prior art, a programming (i.e., writing) operation is performed on each dummy cell after each erasing operation in order to prevent the dummy cell from being over-erased. However, it needs a few program/erase cycles to do the task. However, the programming procedure is not simple. That is, it still needs a few steps Therefore, we need a better method to solve the problem.